Orthogone Technologies is a Quebec electronic-product engineering company providing embedded software, FPGA design, signal processing, edge computing and custom hardware development for aerospace, defence, security, telecommunications and other regulated sectors.
Operating context
Orthogone combines custom FPGA and embedded-system engineering with licensable networking and data-movement IP. Its October 2026 portfolio offers Ethernet MAC/PCS from 1G to 100G, optional FEC at selected rates, hardware TCP/IP and UDP/IP offload, and PCIe Gen3/Gen4 circular-buffer DMA. The kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches and Linux drivers; licensing can be scoped by project, site, company, year or card.
Product layers matter. The new IP portfolio is offered on AMD UltraScale+ and Versal, while the separate ULL Framework page still lists specific Alveo reference boards as current and Versal V80 on its roadmap. MAC, offload and host-transfer latency figures measure different paths, not an end-to-end mission workload.
Altera independently hosts Orthogone’s architecture, optimization, verification and co-development service offering. The January 2026 non-exclusive Convergence alliance, supported by STL Engineering, provides a route to coordinated rugged electronics and thermal/mechanical packaging. Neither a partner listing nor the alliance establishes qualification of a particular finished system.
Canadian footprint
Orthogone Technologies has a documented Canadian operating presence in Saint-Laurent, Quebec, Canada. Its public organization and capability evidence should be read at that location and national scope only where the cited sources explicitly support it.
Saint-Laurent, Quebec is the published city-level context for Orthogone Technologies. It does not imply a street address or exact facility location.
Orthogone offers two useful entry points: engineering capacity for a custom embedded system and a licensable FPGA networking kit that can reduce foundational protocol work. The October portfolio makes interfaces and license scope more concrete, while Altera’s service listing and the Convergence/STL alliance identify complementary engineering routes. A technical discussion should first fix the intended IP blocks, board and software environment, then ask for workload-level latency and qualification evidence. Component benchmarks and historical financing support context but do not prove a finished defence system.
Interpretation of the public record. Not qualification, endorsement or evidence of buyer interest.
Custom FPGA, embedded and electronic-system engineering
Read technical summary
Orthogone combines FPGA and embedded-system engineering with a licensed ultra-low-latency framework. The framework supplies Ethernet MAC/PCS, TCP/UDP offload, PCIe DMA, Linux drivers and a C/C++ interface for host-to-FPGA integration. Current reference designs support AMD Alveo X3522pv and UL3524; Versal V80 support is listed on the roadmap. Published component and host-transfer latency figures measure different paths and should not be treated as end-to-end application performance. Altera’s partner listing corroborates its FPGA engineering service offering.
Evidence of maturity
Commercial engineering and licensable IP offering. Altera lists the development service; a January 2026 non-exclusive Convergence alliance adds a packaging/integration route without certifying a finished system.
Commercial availability
Project, site, annual or per-card licensing and custom engineering are marketed. Confirm target FPGA, source/IP terms, host environment, measured processing path and design-assurance requirements.
Core features
10G MAC/PCS and TCP/UDP offload IP
PCIe DMA with Linux drivers and C/C++ integration
Current Alveo X3522pv and UL3524 reference designs
Orthogone’s licensable FPGA portfolio combines Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G, hardware TCP/IP and UDP/IP offload, and PCIe Gen3/Gen4 circular-buffer DMA. Optional Reed-Solomon FEC is listed at selected Ethernet rates. The integrated kit supplies encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and documentation. The portfolio is offered for evaluation and licensing on AMD UltraScale+ and Versal platforms; a chosen board, protocol configuration and host software environment still define the integration scope.
Evidence of maturity
Orthogone says the IP originated in production FinTech use and reports unnamed adopters in other industries. These supplier statements do not establish a particular defence-system acceptance or end-to-end mission-performance result.
Commercial availability
Available for evaluation and licensing on AMD UltraScale+ and Versal platforms. Project, site, corporate, annualized and card-based terms are offered; confirm the exact board, IP blocks and driver/reference-design deliverables.
Core features
1G to 100G Ethernet MAC/PCS with optional FEC at selected rates
Hardware Layer 2–4 TCP/IP and UDP/IP offload
Bidirectional PCIe Gen3/Gen4 circular-buffer DMA
Encrypted RTL, reference designs, simulation and Linux drivers
Public record
Recent activity
Oct 1, 2026
Orthogone announced on October 1, 2026 that its Ultra-Low-Latency FPGA IP Portfolio is available for evaluation and licensing beyond FinTech on AMD UltraScale+ and Versal platforms. The kit combines Ethernet MAC/PCS, hardware TCP/IP and UDP/IP offload, and PCIe Gen3/Gen4 circular-buffer DMA, with encrypted RTL, reference designs, simulation and Linux drivers.
NRC current agreement 1034393 lists an Agreement Value of C$410,000 for FPGA SmartNIC acceleration, with a period of September 1, 2025 to July 17, 2026. Its January 6, 2026 amendment information separately labels C$70,000; do not add that amount again to the headline value. Desjardins’ April 2022 minority-equity and share-buyback financing announcement discloses no amount. These records do not establish revenue, current cash or final project acceptance.
Ownership and entity scope
Desjardins announced a minority equity investment in April 2022. The current ownership percentage and complete cap table are not established by the reviewed public records.
Ecosystem relationships
Announced minority equity investor
Desjardins Capital
Desjardins announced on April 12, 2022 that it became a strategic partner and minority shareholder in Orthogone through growth-capital and share-buyback financing. No round amount or current ownership percentage is established by that announcement.
IRAP contribution recipient
National Research Council Canada
NRC current agreement 1034393 lists C$410,000 for FPGA-based SmartNIC host-processor and network acceleration, covering September 1, 2025 to July 17, 2026. The record includes a January 6 amendment with separately labelled C$70,000 information; the headline agreement value is not evidence of cash received or final deliverable acceptance.
Orthogone and Convergence announced a January 21, 2026 non-exclusive alliance for defence and automotive engineering, coordinating embedded hardware, software and rugged electronics. STL Engineering supports thermal/mechanical analysis and packaging. This is a services relationship rather than product certification.
Reviewed connections
Mission area · Reviewed connectionEvidence strength: Moderate
FPGA-based real-time processing and embedded systems could support low-latency sensor and communications workloads at the edge; this is a derived mission mapping.
Questions for a first conversation
01
Which IP portfolio blocks, framework version, reference board and driver environment are included in the proposed license and evaluation?
The portfolio offers AMD UltraScale+ and Versal support, while the separate Framework page keeps a specific Versal V80 board on its roadmap. Scope and deliverables should be confirmed together.
02
What measured end-to-end workload latency and environmental/design-assurance evidence apply to the integrated mission system?
Published MAC, offload and DMA benchmarks measure different paths. The Convergence/STL alliance adds engineering capabilities without establishing qualification of a particular finished system.
Original sources 13 linked records
These records support the organization, its owned capabilities and their reviewed connections. A source count is not a count of independent confirmations.
Orthogone’s ULL FPGA framework provides licensed RTL/IP blocks for Ethernet MAC/PCS, TCP/UDP, PCIe DMA and Linux C/C++ integration. Supported AMD Alveo boards are distinguished from Versal V80 roadmap work. Its nanosecond MAC figures and roughly 585–635 ns DMA figures measure different layers and are not end-to-end mission processing latency.
Supports: Profile · operating context
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Orthogone’s ULL FPGA framework provides licensed RTL/IP blocks for Ethernet MAC/PCS, TCP/UDP, PCIe DMA and Linux C/C++ integration. Supported AMD Alveo boards are distinguished from Versal V80 roadmap work. Its nanosecond MAC figures and roughly 585–635 ns DMA figures measure different layers and are not end-to-end mission processing latency.
Altera hosts an Orthogone FPGA development services listing covering architecture, optimization, verification, turnkey development, co-development and resource augmentation.
Supports: Profile · operating context
Altera hosts an Orthogone FPGA development services listing covering architecture, optimization, verification, turnkey development, co-development and resource augmentation.
Orthogone and Convergence Design Services announced an engineering alliance spanning FPGA/embedded design and rugged, thermally managed hardware with STL Engineering. The collaboration targets defence and automotive programmes; an alliance does not itself certify an integrated product.
Supports: Profile · operating context
The alliance describes coordinated development, validation and long-term support. It does not identify a particular finished system as qualified to all referenced MIL-STD or DO-160 standards.
An Open Government record describes a 2025-2026 NRC-supported project for ultra-low-latency FPGA SmartNIC functions, while Orthogone's current Altera partner page describes aerospace and defence FPGA applications.
Supports: Profile · current activity
An Open Government record describes a 2025-2026 NRC-supported project for ultra-low-latency FPGA SmartNIC functions, while Orthogone's current Altera partner page describes aerospace and defence FPGA applications.
Orthogone Technologies has a documented Canadian operating presence in Saint-Laurent, Quebec.
Supports: Profile · description
Orthogone Technologies is a Quebec electronic-product engineering company providing embedded software, FPGA design, signal processing, edge computing and custom hardware development for aerospace, defence, security, telecommunications and other regulated sectors.
Public sources cited · Facts and assessments kept separate · Human review
FPGA and embedded-systems engineering may help teams working on Major-event and critical-infrastructure cyber defence by contributing to detection and situational awareness, resilient communications and command, and cyber and digital operations.
FPGA and embedded-systems engineering may help teams working on Sovereign defence capability areas by contributing to detection and situational awareness, cyber and digital operations, and aerospace operations.
Reviewed connections indicate possible relevance based on public evidence. They do not indicate procurement direction, eligibility, endorsement or customer interest.
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Orthogone’s ULL FPGA framework provides licensed RTL/IP blocks for Ethernet MAC/PCS, TCP/UDP, PCIe DMA and Linux C/C++ integration. Supported AMD Alveo boards are distinguished from Versal V80 roadmap work. Its nanosecond MAC figures and roughly 585–635 ns DMA figures measure different layers and are not end-to-end mission processing latency.
Supports: Profile · executive relevance summary
Source location: executiveRelevanceSummary
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Orthogone’s ULL FPGA framework provides licensed RTL/IP blocks for Ethernet MAC/PCS, TCP/UDP, PCIe DMA and Linux C/C++ integration. Supported AMD Alveo boards are distinguished from Versal V80 roadmap work. Its nanosecond MAC figures and roughly 585–635 ns DMA figures measure different layers and are not end-to-end mission processing latency.
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Framework benchmarks list 10G MAC/PCS wire-to-wire round trips of 17.1 ns (16 bit) and 34.1 ns (32 bit), 6.2 ns TX offload, and host-dependent PCIe DMA of 585–635 ns. These measure different layers and host systems.
Orthogone’s ULL FPGA framework provides licensed RTL/IP blocks for Ethernet MAC/PCS, TCP/UDP, PCIe DMA and Linux C/C++ integration. Supported AMD Alveo boards are distinguished from Versal V80 roadmap work. Its nanosecond MAC figures and roughly 585–635 ns DMA figures measure different layers and are not end-to-end mission processing latency.
Supports: FPGA and embedded-systems engineering · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · commercial availability
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · capability type
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · maturity
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · summary
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · name
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering · technology readiness level
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: FPGA and embedded-systems engineering → Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Orthogone and Convergence Design Services announced an engineering alliance spanning FPGA/embedded design and rugged, thermally managed hardware with STL Engineering. The collaboration targets defence and automotive programmes; an alliance does not itself certify an integrated product.
The alliance describes coordinated development, validation and long-term support. It does not identify a particular finished system as qualified to all referenced MIL-STD or DO-160 standards.
The alliance describes coordinated development, validation and long-term support. It does not identify a particular finished system as qualified to all referenced MIL-STD or DO-160 standards.
Orthogone and Convergence Design Services announced an engineering alliance spanning FPGA/embedded design and rugged, thermally managed hardware with STL Engineering. The collaboration targets defence and automotive programmes; an alliance does not itself certify an integrated product.
The alliance describes coordinated development, validation and long-term support. It does not identify a particular finished system as qualified to all referenced MIL-STD or DO-160 standards.
Supports: Profile · operating context
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
Orthogone and Convergence Design Services announced an engineering alliance spanning FPGA/embedded design and rugged, thermally managed hardware with STL Engineering. The collaboration targets defence and automotive programmes; an alliance does not itself certify an integrated product.
Orthogone and Convergence Design Services announced an engineering alliance spanning FPGA/embedded design and rugged, thermally managed hardware with STL Engineering. The collaboration targets defence and automotive programmes; an alliance does not itself certify an integrated product.
Supports: Profile · executive relevance summary
Source location: executiveRelevanceSummary
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
The alliance describes coordinated development, validation and long-term support. It does not identify a particular finished system as qualified to all referenced MIL-STD or DO-160 standards.
Supports: FPGA and embedded-systems engineering · maturity
Orthogone January21 2026 announces non-exclusive alliance with Convergence Design Services and associated mechanical integration expertise for defence/automotive programmes; it is an engineering partnership, not a named delivery contract.
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
Orthogone and Convergence announced a non-exclusive engineering alliance on January 21, 2026 for defence and automotive programmes, with STL Engineering providing thermal/mechanical analysis and rugged packaging support.
Supports: Profile · disclosed financing summary
The NRC record shows one amendment dated January 6, 2026 and separately labels its total amended value as CAD 70,000. The headline Agreement Value is CAD 410,000.
Supports: Profile · operating context
Open Government records a $340,000 NRC contribution for Orthogone to develop FPGA-based SmartNIC acceleration and ultra-low-latency network functions.
Supports: Profile · disclosed financing summary
NRC current agreement 1034393 lists an Agreement Value of CAD 410,000 for FPGA SmartNIC host-processor/network acceleration, with an agreement period of September 1, 2025 to July 17, 2026.
Supports: Profile · current activity as of
Open Government Canada supports 2025-09-01 as the material date used for this dossier activity note.
Supports: Profile · profileData.currentActivity
An Open Government record describes a 2025-2026 NRC-supported project for ultra-low-latency FPGA SmartNIC functions, while Orthogone's current Altera partner page describes aerospace and defence FPGA applications.
NRC current agreement 1034393 lists an Agreement Value of CAD 410,000 for FPGA SmartNIC host-processor/network acceleration, with an agreement period of September 1, 2025 to July 17, 2026.
NRC current agreement 1034393 lists an Agreement Value of CAD 410,000 for FPGA SmartNIC host-processor/network acceleration, with an agreement period of September 1, 2025 to July 17, 2026.
NRC current agreement 1034393 lists an Agreement Value of CAD 410,000 for FPGA SmartNIC host-processor/network acceleration, with an agreement period of September 1, 2025 to July 17, 2026.
NRC current agreement 1034393 lists an Agreement Value of CAD 410,000 for FPGA SmartNIC host-processor/network acceleration, with an agreement period of September 1, 2025 to July 17, 2026.
The NRC record shows one amendment dated January 6, 2026 and separately labels its total amended value as CAD 70,000. The headline Agreement Value is CAD 410,000.
The official public contact pathway for Orthogone Technologies is https://orthogone.com/.
Supports: Profile · operating context
Orthogone Technologies is a Quebec electronic-product engineering company providing embedded software, FPGA design, signal processing, edge computing and custom hardware development for aerospace, defence, security, telecommunications and other regulated sectors.
Supports: Profile · editorial profile version
Orthogone Technologies has sufficient mapped public evidence for private reviewer consideration of the shared editorial profile template.
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Profile · current activity
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Profile · operating context
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Profile · current activity
Orthogone combines hardware Layer 2–4 TCP/IP and UDP/IP offload with bidirectional PCIe Gen3/Gen4 circular-buffer DMA for FPGA-to-host data movement.
Supports: Profile · operating context
Orthogone combines hardware Layer 2–4 TCP/IP and UDP/IP offload with bidirectional PCIe Gen3/Gen4 circular-buffer DMA for FPGA-to-host data movement.
Supports: Profile · current activity as of
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Profile · current activity
The new portfolio lists IEEE 802.3 Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G, with optional Reed-Solomon FEC at 25G and 100G.
Supports: Profile · executive relevance summary
Source location: executiveRelevanceSummary
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Profile · operating context
The new portfolio lists IEEE 802.3 Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G, with optional Reed-Solomon FEC at 25G and 100G.
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · summary
Orthogone combines hardware Layer 2–4 TCP/IP and UDP/IP offload with bidirectional PCIe Gen3/Gen4 circular-buffer DMA for FPGA-to-host data movement.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · commercial availability
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · maturity
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · summary
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · summary
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · name
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technical tags
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · commercial availability
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
The new portfolio lists IEEE 802.3 Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G, with optional Reed-Solomon FEC at 25G and 100G.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · capability type
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technology readiness level
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technicaldomainslugs
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technical tags
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technical tags
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
The portfolio kit includes encrypted RTL, AMD Alveo reference designs, simulation testbenches, Linux drivers and product documentation, with project, site, corporate, annual and card licensing options.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · summary
The new portfolio lists IEEE 802.3 Ethernet MAC/PCS at 1G, 10G, 25G, 40G and 100G, with optional Reed-Solomon FEC at 25G and 100G.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technicaldomainslugs
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone combines hardware Layer 2–4 TCP/IP and UDP/IP offload with bidirectional PCIe Gen3/Gen4 circular-buffer DMA for FPGA-to-host data movement.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · maturity
Orthogone says the IP originated in production FinTech applications and reports unnamed early adopters beyond FinTech, including aerospace, defence and quantum computing. No named mission-system acceptance is disclosed.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · defence applications
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · defence applications
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · defence applications
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone combines hardware Layer 2–4 TCP/IP and UDP/IP offload with bidirectional PCIe Gen3/Gen4 circular-buffer DMA for FPGA-to-host data movement.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · slug
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · core features
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
Supports: Ultra-Low-Latency FPGA networking IP portfolio · technical tags
Orthogone announced on October 1, 2026 that its ULL FPGA IP Portfolio is available for evaluation and licensing on AMD UltraScale+ and Versal adaptive platforms.
True North Map derives this first-conversation question from the documented Orthogone Technologies capability, current evidence and the decision gap that remains.
Orthogone Technologies's public evidence establishes its current role and offering, but it does not answer every access, configuration, eligibility, maturity or buyer question needed for a first business-development conversation.
Supports: Profile · operating context
FPGA and SoC design; Embedded software and hardware; Real-time signal processing; Sensor, communications and radar engineering
Supports: FPGA and embedded-systems engineering · summary
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Supports: FPGA and embedded-systems engineering → Edge Data Processing
FPGA-based real-time processing and embedded systems could support low-latency sensor and communications workloads at the edge; this is a derived mission mapping.
Supports: FPGA and embedded-systems engineering → Major-event and critical-infrastructure cyber defence
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Supports: FPGA and embedded-systems engineering → Sovereign defence capability areas
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Orthogone publishes 2250 Alfred-Nobel Boulevard, Suite 500, Saint-Laurent, Quebec, H4S 2C9; main phone 514-316-1917; and organization-wide info@orthogone.com and sales@orthogone.com addresses.
Orthogone publishes 2250 Alfred-Nobel Boulevard, Suite 500, Saint-Laurent, Quebec, H4S 2C9; main phone 514-316-1917; and organization-wide info@orthogone.com and sales@orthogone.com addresses.
Orthogone publishes 2250 Alfred-Nobel Boulevard, Suite 500, Saint-Laurent, Quebec, H4S 2C9; main phone 514-316-1917; and organization-wide info@orthogone.com and sales@orthogone.com addresses.
Orthogone publishes 2250 Alfred-Nobel Boulevard, Suite 500, Saint-Laurent, Quebec, H4S 2C9; main phone 514-316-1917; and organization-wide info@orthogone.com and sales@orthogone.com addresses.
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: Profile · disclosed financing summary
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: Announced minority equity investor relationship
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: Announced minority equity investor relationship
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: Announced minority equity investor relationship
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: Announced minority equity investor relationship
On April 12, 2022 Desjardins announced it became an Orthogone strategic partner and minority shareholder through a growth-capital and share-buyback financing round. No investment amount was disclosed.
Supports: FPGA and embedded-systems engineering · summary
Altera partner offering lists Orthogone FPGA architecture, optimization, verification and turnkey/co-development services; directory presence supports an engineering-service route, not independent timing benchmarks or product certification.
Supports: FPGA and embedded-systems engineering · maturity
Altera partner offering lists Orthogone FPGA architecture, optimization, verification and turnkey/co-development services; directory presence supports an engineering-service route, not independent timing benchmarks or product certification.
Supports: FPGA and embedded-systems engineering → Major-event and critical-infrastructure cyber defence
High-profile events and their host organizations create concentrated cyber-risk and require coordinated planning, monitoring, incident response, exercises and secure information sharing across federal, provincial, municipal and private partners.
Supports: FPGA and embedded-systems engineering → Major-event and critical-infrastructure cyber defence
Reviewer synthesis of the public end state in the cited material: Event partners should be able to prepare for, detect and respond to cyber incidents through integrated threat intelligence, technical support, exercises and operational coordination before and during major events.
Supports: FPGA and embedded-systems engineering → Sovereign defence capability areas
Reviewer synthesis of the public end state: Canada can build, sustain or control priority aerospace, ammunition, digital, in-service support, sensor, space, specialized manufacturing, training and uncrewed capabilities through domestic strength, trusted partnerships and sovereign access.
Supports: FPGA and embedded-systems engineering → Sovereign defence capability areas
Canada needs secure strategic autonomy and reliable access to capabilities that are critical to defending its sovereignty and meeting allied commitments, while reducing exposure to foreign supply-chain and intellectual-property dependencies.
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