Orthogone combines FPGA and embedded-system engineering with a licensed ultra-low-latency framework. The framework supplies Ethernet MAC/PCS, TCP/UDP offload, PCIe DMA, Linux drivers and a C/C++ interface for host-to-FPGA integration. Current reference designs support AMD Alveo X3522pv and UL3524; Versal V80 support is listed on the roadmap. Published component and host-transfer latency figures measure different paths and should not be treated as end-to-end application performance. Altera’s partner listing corroborates its FPGA engineering service offering.
Technical detail
Core features
10G MAC/PCS and TCP/UDP offload IP
PCIe DMA with Linux drivers and C/C++ integration
Current Alveo X3522pv and UL3524 reference designs
Versal V80 support remains on the roadmap
FPGA
Embedded systems
Signal processing
Edge computing
Radar
Use & integration
Recorded applications
Aerospace and defence electronics
Radar and communications systems
Edge AI and sensor processing
Secure and safety-critical product development
These describe the reviewed application scope, not confirmed deployments, released requirements or procurement eligibility.
Evidence of maturity
Commercial engineering and licensable IP offering. Altera lists the development service; a January 2026 non-exclusive Convergence alliance adds a packaging/integration route without certifying a finished system.
Commercial availability
Project, site, annual or per-card licensing and custom engineering are marketed. Confirm target FPGA, source/IP terms, host environment, measured processing path and design-assurance requirements.
Integration and verification
Readiness
A technology readiness level is not established by the reviewed public sources.
FPGA-based real-time processing and embedded systems could support low-latency sensor and communications workloads at the edge; this is a derived mission mapping.
FPGA and embedded-systems engineering may help teams working on Sovereign defence capability areas by contributing to detection and situational awareness, cyber and digital operations, and aerospace operations.
These records support this capability and its published Mission area and Defence need connections. A source count is not a count of independent confirmations.
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · commercial availability
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · capability type
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · maturity
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · summary
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · core features
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · defence applications
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technicaldomainslugs
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · name
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technical tags
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Capability · technology readiness level
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Edge Data Processing
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Supports: Mission area · Autonomous Patrol and Monitoring
Orthogone ULL framework delivers encrypted 10G MAC/PCS, TCP/UDP and PCIe DMA RTL plus Linux C/C++ drivers/APIs; current Alveo X3522pv/UL3524, Versal V80 and Ryzen remain roadmap/future. Component MAC17.1/34.1ns, TX6.2ns and host-DMA585–635ns are separate measurements, not end-to-end mission latency.
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Supports: Mission area · Edge Data Processing
FPGA-based real-time processing and embedded systems could support low-latency sensor and communications workloads at the edge; this is a derived mission mapping.
Supports: Defence need · Sovereign defence capability areas
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Altera partner offering lists Orthogone FPGA architecture, optimization, verification and turnkey/co-development services; directory presence supports an engineering-service route, not independent timing benchmarks or product certification.
Supports: Capability · maturity
Altera partner offering lists Orthogone FPGA architecture, optimization, verification and turnkey/co-development services; directory presence supports an engineering-service route, not independent timing benchmarks or product certification.
Orthogone January21 2026 announces non-exclusive alliance with Convergence Design Services and associated mechanical integration expertise for defence/automotive programmes; it is an engineering partnership, not a named delivery contract.
Supports: Defence need · Sovereign defence capability areas
Reviewer synthesis of the public end state: Canada can build, sustain or control priority aerospace, ammunition, digital, in-service support, sensor, space, specialized manufacturing, training and uncrewed capabilities through domestic strength, trusted partnerships and sovereign access.
Public sources cited · Facts and assessments kept separate · Human review
FPGA and embedded-systems engineering may help teams working on Major-event and critical-infrastructure cyber defence by contributing to detection and situational awareness, resilient communications and command, and cyber and digital operations.
This is a reviewed public-source assessment. It is not procurement eligibility, endorsement, customer interest, or classified demand.
Supports: Defence need · Major-event and critical-infrastructure cyber defence
Orthogone develops custom FPGA, embedded-computing and electronic-product solutions, including communications, radar, signal-processing and real-time systems for harsh, safety-critical and regulated environments.
Supports: Defence need · Sovereign defence capability areas
Canada needs secure strategic autonomy and reliable access to capabilities that are critical to defending its sovereignty and meeting allied commitments, while reducing exposure to foreign supply-chain and intellectual-property dependencies.
Supports: Defence need · Major-event and critical-infrastructure cyber defence
High-profile events and their host organizations create concentrated cyber-risk and require coordinated planning, monitoring, incident response, exercises and secure information sharing across federal, provincial, municipal and private partners.
Supports: Defence need · Major-event and critical-infrastructure cyber defence
Reviewer synthesis of the public end state in the cited material: Event partners should be able to prepare for, detect and respond to cyber incidents through integrated threat intelligence, technical support, exercises and operational coordination before and during major events.
